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asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 1 - general description the AK4703 offers the ideal features for digital set-top-box systems. the AK4703 includes the audio switches, video switches, video filters, etc. designed primarily for digital set-top-box systems. the AK4703 is offered in a space saving 64-pin lqfp package. features analog switches for scart audio section ? thd+n: ? 86db (@2vrms) ? dynamic range: 96db (@2vrms) ? six analog inputs full differential ster eo input for decoder dac two stereo input (tv & vcr scart) ? five analog outputs two stereo outputs (tv & vcr scart) one mono output (modulator) ? pop noise free circuit for power on/off video section ? integrated lpf: ? 35db@27mhz ? 75ohm driver ? 6db gain for outputs ? four cvbs/y inputs (encx2, tv, vcr) three cvbs/y output s (rf, tv, vcr) ? three r/c inputs (encx2, vcr) , two r/c output (tv, vcr) ? bi-directional control for vcr-chroma/red ? two g and b inputs (enc, vcr), one g and b outputs (tv) ? tv/vcr input monitor loop-through mode for standby auto-startup mode for power saving scart pin#tbd(fast blanking), pin#tbd(slow blanking) control power supply ? 5v+/ ? 5% and 12v+/ ? 5% ? low power dissipation / low power standby mode package ? 64pin lqfp a v scart switch AK4703 = target spec =
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 2 - ? block diagram tvoutl monoout tvoutr vcroutl vcroutr tvinl t vinr vcrinl vcrinr a inl+ a inl- a inr- a inr+ bias tv1-0 msel mono sck sda register control pdn vcom12 vd vcr1-0 vcoml lin vmono a mpl a mpr rin vcom5 vp vss amp vcomr refi vvss audio block
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 3 - enc c tvrc enc g/cvbs vcr g tvg enc b vcr b tvb enc y tvvout rfv 6db 6db 6db 6db enc r/c vcrvout vcrc 6db 6db vcr cvbs/ y tv cvbs vcr r/c enc cvbs/y encc encg vcrg encb vcrb ency encrc vcrvin tvvin vcrrc encv ( typical connection ) rf mod tv scart vcr scart ( typical connection ) vvd2 vvss vvd1 6db monitor video block monitor vcr fb tvfb 6db 0v 2v tvsb vcrsb 0/ 6/ 12v 0/ 6/ 12v vcrfb ( typical connection ) tv scart vcr scart ( typical connection ) int video blanking block
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 4 - ? ordering guide AK4703vq ? 10 +70 c 64pin lqfp (0.5mm pitch) ? pin layout tbd
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 5 - pin/function (tbd) no. pin name i/o function 1 vcrc o chrominance output pin for vcr 2 vvss - video ground pin, 0v 3 tvvout o composite/luminance output pin for tv 4 vvd2 - video power supply pin #2, 5v normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 5 tvrc o red/chrominance output pin for tv 6 tvg o green output pin for tv 7 tvb o blue output pin for tv 8 vvd1 - video power supply pin #1, 5v normally connected to vvss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 9 encb i blue input pin for encoder 10 encg i green input pin for encoder 11 encrc i red/chrominance input pin1 for encoder 12 encc i chrominance input pin2 for encoder 13 encv i composite/luminance input pin1 for encoder 14 ency i composite/luminance input pin2 for encoder 15 tvvin i composite/luminance input pin for tv 16 vcrvin i composite/luminance input pin for vcr 17 vcrfb i fast blanking input pin for vcr 18 vcrrc i red/chrominance input pin for vcr 19 vcrg i green input pin for vcr 20 vcrb i blue input pin for vcr 21 int o interrupt pin for video blanking 22 vcrsb i/o slow blanking input/output pin for vcr 23 tvsb o slow blanking output pin for tv 24 vcrinr i rch vcr audio input pin 25 vcrinl i lch vcr audio input pin 26 tvinr i rch tv audio input pin 27 tvinl i lch tv audio input pin 28 tbd 29 vcroutr o rch analog output pin1 30 vcroutl o lch analog output pin1 31 tvoutr o rch analog output pin2 32 tvoutl o lch analog output pin2 pin layout is tbd.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 6 - pin/function (tbd, continued) no. pin name i/o function 33 vss - ground pin, 0v 34 vd - power supply pin, 5v normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 35 lin i lch input pin 36 ampl o lch feed back resistor output pin 37 ainl+ i lch positive analog input pin 38 ainl ? i lch negative analog input pin 39 rin i rch input pin 40 ampr o rch feed back resistor output pin 41 ainr+ i rch positiv e analog input pin 42 ainr ? i rch negative analog input pin 43 scl i control data clock pin 44 sda i/o control data pin 45 pdn i power-down mode pin when at ?l?, the AK4703 is in the power-down mode and is held in reset. the AK4703 should always be reset upon power-up. 46 rfv o composite output pin for rf modulator 47 vcrvout o composite/luminance output pin for vcr 48 tvfb o fast blanking output pin for tv 49 monoout o mono analog output pin 50 vp - power supply pin, 12v normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 51 vcom5 o common voltage pin normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. 52 vcom12 o audio common voltage pin normally connected to vss with a 0.1 f ceramic capacitor in parallel with a 10 f electrolytic cap. the caps affect the settling time of audio bias level. 53 vcomo o common voltage output pin 54 refi i tbd 55 tbd 56 tbd 57 tbd 58 tbd 59 tbd 60 tbd 61 tbd 62 tbd 63 tbd 64 tbd note: all input pins should not be left floating. pin layout is tbd.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 7 - absolute maximum ratings (vss = vvss = 0v; note 1) parameter symbol min max units power supply vd vvd1 vvd2 vp |vss ? vvss| (note 2) ? 0.3 ? 0.3 ? 0.3 ? 0.3 - 6.0 6.0 6.0 14 0.3 v v v v v input current (any pins except for supplies) iin - 10 ma input voltage vind ? 0.3 vd+0.3 v video input voltage vinv ? 0.3 vvd1+0.3 v audio input voltage (except lin, rin, ainl+/ ? , ainr+/ ? pins) vina ? 0.3 vp+0.3 v audio input voltage (except lin, rin, ainl+/ ? , ainr+/ ? pins) vina ? 0.3 vd+0.3 v ambient operating temperature ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. vss and vvss must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss = vvss = 0v; note 1) parameter symbol min typ max units power supply vd vvd1=vvd2 vp 4.75 4.75 11.4 5.0 5.0 12 5.25 5.25 12.6 v v v note 3. analog output voltage scales with the voltage of vd. aout (typ@0db) = 2vrms vd/5. *akm assumes no responsibility for the usage beyond the conditions in this datasheet. electrical characteristics (ta = 25 c; vp = 12v, vd = 5v; vvd1 = vvd2 = 5v) power supplies min typ max units power supply current normal operation (pdn = ?h?) (note 4) vd vvd1+vvd2 vp power-down mode (pdn = ?l?) (note 5) vd vvd1+vvd2 vp tbd tbd tbd 10 10 10 tbd tbd tbd 100 100 100 ma ma ma a a a note 4. stby bit = ?l?, all video outputs active. no signal, no load for a/v switches. note 5. all digital inputs are held at vd or vss.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 8 - digital characteristics (ta = 25 c; vd = 4.75 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.0 - - - - 0.8 v v low-level output voltage (sda pin: iout= 3ma, int pin: iout= 1ma) vol - - 0.4 v input leakage current iin - - 10 a analog characteristics (audio) (ta = 25 c; vp = 12v, vd = 5v; vvd1 = vvd2 = 5v; signal frequency = 1khz; measurement frequency = 20hz 20khz; r l 4.5k ? ; 0db=2vrms output; unless otherwise specified) parameter min typ max units analog input: (tvinl/tvinr/vcrinl/vcrinr pins) analog input characteristics input voltage 2 vrms input resistance 100 150 - k ? analog input: (lin/rin pins) analog input characteristics input voltage 1 vrms input resistance 40 60 - k ? stereo/mono output: (tvoutl/tvoutr/vcroutl/vcroutr/monoout pins) (note 6) analog output characteristics thd+n (at 2vrms output) (note 7) ? 86 ? 80 db dynamic range ( ? 60db output, a-weighted) (note 7) 92 96 db s/n (a-weighted) (note 7) 92 96 db interchannel isolation (note 7, 8) 80 90 db interchannel gain mismatch (note 7, 8) - 0.3 - db gain drift - 200 - ppm/ c load resistance (ac-lord, note 10) tvoutl/r, vcroutl/r, monoout 4.5 k ? output voltage (note 9, 10) 1.85 2 2.15 vrms power supply rejection (psr) (note 11) - 50 db note 6. measured by audio precision system two cascade. note 7. analog in to tvout. path : ainl+/ ? (ainr+/ ? ) tvoutl (tvoutr) note 8. between tvoutl and tvoutr with analog inputs (ainl/r+/ ? ) 1khz/0db. note 9. thd+n : ? 80db(min. at 2vrns). note 10. analog input voltage by lin/rin pins (0db). stereo output (typ@0dbfs) = 2vrms vd/5. do not output signals over 3vrms. note 11. the psr is applied to vd with 1khz, 100mv. filter characteristics (ta = 25 c; vp = 11.4 12.6v, vd = 4.75 5.25v, vvd1 = vvd2 = 4.75 5.25v) parameter symbol min typ max units lpf frequency response 0 20.0khz fr - 0.5 - db
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 9 - analog characteristics (video) (ta = 25 c; vp = 12v, vd = 5v; vvd1 = vvd2 = 5v; unless otherwise specified.) parameter conditions min typ max units sync tip clamp voltage at output pin. 0.7 v chrominance bias voltage at output pin. 2.2 v gain input = 0.3vp-p, 100khz 5.5 6 6.5 db interchannel gain mismatch tvrc, tvg, tvb. input = 0.3vp-p, 100khz. ? 0.3 - 0.3 db frequency response input=0.3vp-p, c1=c2=0pf. 100khz to 6mhz. at 12mhz. at 27mhz. ? 1.0 ? 3 ? 35 0.5 tbd db db db group delay distortion at 4.43mhz with respect to 1mhz. 15 ns input impedance chrominance input (internally biased) 40 60 - k ? input signal f = 100khz, maximum with distortion < 1.0%, gain = 6db. - - 1.5 vpp load resistance (note 12) 150 - - ? load capacitance c1 (note 12) c2 (note 12) 400 15 pf pf dynamic output signal f = 100khz, maximum with distortion < 1.0% - - 3 vpp y/c crosstalk f = 4.43mhz, 1vp-p input. among tvvout, tvrc, vcrvout and vcrc outputs. - ? 50 - db s/n reference level = 0.7vp-p, ccir 567 weighting. bw = 15khz to 5mhz. - 74 - db differential gain 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - tbd - % differential phase 0.7vpp 5steps modulated staircase. chrominance &burst are 280mvpp, 4.43mhz. - tbd - degree note 12. refer the figure 1. video signal output 75 ohm 75 ohm max: 400pf c1 r1 r2 max: 15pf c2 figure 1. load resistance r1+r2 and load capacitance c1/c2.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 10 - switching characteristics (ta = 25 c; vp = 11.4 12.6v, vd = 4.75 5.25v, vvd1 = vvd2 = 4.75 5.25v; c l = 20pf) parameter symbol min typ max units control interface timing (i 2 c bus): scl clock frequency bus free time between transmissions start condition hold time (prior to first clock pulse) clock low time clock high time setup time for repeated start condition sda hold time from scl falling (note 13) sda setup time from scl rising rise time of both sda and scl lines fall time of both sda and scl lines setup time for stop condition pulse width of spike noise suppressed by input filter fscl tbuf thd:sta tlow thigh tsu:sta thd:dat tsu:dat tr tf tsu:sto tsp - 1.3 0.6 1.3 0.6 0.6 0 0.1 - - 0.6 0 400 - - - - - - - 0.3 0.3 - 50 khz s s s s s s s s s s ns reset timing pdn pulse width (note 14) tpd 150 ns note 13. data must be held for sufficient time to bridge the 300 ns transition time of scl. note 14. the AK4703 should be reset by pdn pin = ?l? upon power up. note 15. i 2 c is a registered trademark of philips semiconductors. purchase of asahi kasei microsystems co., ltd i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system, provided the system conform to the i 2 c specifications defined by philips.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 11 - ? timing diagram thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp i 2 c bus mode timing tpd vil pdn power-down timing
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 12 - operation overview 1. system reset and power-down options the AK4703 should be reset once by bringing pdn pin = ?l? upon power-up. the AK4703 has several operation modes. the pdn pin, auto bit, bias bit, stby bit and amp bit control operation modes as shown in table 1 and table 2 mode pdn pin auto bit stby bit bias bit amppd bit mode 0 ?l? * * * * full power-down 1 ?h? 1 * * * auto startup mode (power-on default) 2 ?h? 0 1 1 * standby & mute 3 ?h? 0 1 0 * standby 4 ?h? 0 0 1 1 mute (amp power down) 5 ?h? 0 0 1 0 mute (amp operation) 6 ?h? 0 0 0 1 normal operation (amp power down & analog input) 7 ?h? 0 0 0 0 normal operation (amp operation) table 1. operation mode settings (*: don?t care) mode register control audio bias level video output tvfb, tvsb vcrsb 0 full power-down not available no video input power down hi-z hi-z pull-down (*) 1 auto startup mode (power-on default) video input (**) active active (***) 2 standby & mute power down 3 standby active 4 mute (amp power down) 5 mute (amp operation) power down 6 normal operation (amp power down & analog input) 7 normal operation (amp operation) available active (****) hi-z / active active active (*): internally pulled down by 120k ? (typ) resistor. (**): video input to tvvin or vcrvin. (***): vcrc outputs 0v for termination. (****): tvoutl/r are muted by mute bit in the default state. table 2. status of each operation modes
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 13 - ? full power-down mode the AK4703 should be reset once by bringing pdn pin = ?l? upon power-up. pdn pin: power down pin l: device power down. h: normal operation. ? auto startup mode after when the pdn pin is set to ?h?, the AK4703 is in the auto startup mode. in this mode, all blocks except for the video detection circuit are powered down. once the video detection circuit detects video signal from tvvin pin or vcrvin pin, the AK4703 goes to the stand-by mode automatically and sends ?h? pulse via int pin. to exit the auto startup mode, set the auto bit to ?0?. auto bit (00h d3): auto startup bit 0: auto startup disable. (manual startup) 1: auto startup enable. (default) ? amp power-down mode the internal amp block can be powered-down by amppd bit. when amppd bit =?1?, the internal amp block is powered-down. amppd bit (00h d2): amp power-down bit 0: normal operation. 1: amp power-down. (default) ? bias mode when the bias bit = ?1?, the bias voltage on the audio output goes to gnd level. bringing bias bit to ?0? changes this bias voltage smoothly from gnd to vp/2 by 2sec (typ.). this removes the huge click noise related the sudden change of bias voltage at power-on. the change of bias bit from ?1? to ?0? also makes smooth transient from vp/2 to gnd by 2sec (typ). this removes the huge click noise related the sudden change of bias voltage at power-off. bias bit (00h d1): bias-off bit 0: normal operation. 1: set the audio bias to gnd. (default) ? standby mode when the auto bit = bias bit = ?0? and the stby bit = ?1?, the AK4703 is forced into tv-vcr loop through mode. in this mode, the sources of tvoutl/r and monoout pins are fixed to vcrinl/r pins; the sources of vcroutl/r are fixed to tvinl/r pins respectively. all register values themselves are not changed by stby bit = ?1?. stby bit (00h d0): standby bit 0: normal operation. 1: standby mode. (default) ? normal operation mode to change analog switches, set the auto bit, bias bit and stby bit to ?0?. the AK4703 is in power-down mode until pdn pin = ?h?. the figure 2 shows an example of the system timing at the power-down and power-up by pdn pin.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 14 - ? typical operation sequence (auto setup mode) the figure 2 shows an example of the system timing at auto setup mode. pdn pin a udio out (dc) tvvout, vcrvout active (loop-through) tvvin signal in no signal don?t care signal in no signal don?t care vcrvin signal in no signal don?t care don?t care active (loop-through) hi-z hi-z active (loop-through) (gnd) active (loop-through) no signal no signal hi-z low power mode low power mode low power mode figure 2. typical operating sequence (auto setup mode) ? typical operation sequence (except auto setup mode) the figure 3 shows an example of the system timing at auto setup mode. pdn p in ?1? (default) stby bit ?0? ?1? ?1? (default) bias bit ?0? ?stand-by? ?1? ?0? ?stand-by? ?mute? ?1? tv out amp tv-source select vcr in vcr in vcr in (1) vcr in fixed to vcr in(loop-through) (default) offset calibration (2) ?1? (default) a uto bit ?0? notes: (1) mute the analog outputs externally if click noise (1) adversely affects the system. (2) in case of the cal bit = ?1?, the offset calibration is always executed when the source of tvoutl/r pins are switched to amp after the stby bit is changed to ?0?. to disable this function, set the cal bit = ?0?. figure 3. typical operating sequence (except auto setup mode)
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 15 - 2. audio block ? switch control the AK4703 has switch matrixes designed primarily for scart r outing. those are controlled via the control register as shown in, table 3, table 4 and table (please refer to the block diagram). (01h: d1-d0) tv1 tv0 source of tvoutl/r 0 0 amp 0 1 vcrin (default) 1 0 mute 1 1 lin/rin table 3. tvout switch configuration (01h: d2-d0) msel tv1 tv0 source of monoout 0 0 0 amp (l+r)/2 0 0 1 amp (l+r)/2 0 1 0 amp (l+r)/2 0 1 1 (reserved) 1 0 0 amp (l+r)/2 1 0 1 vcrin (l+r)/2 1 1 0 mute 1 1 1 (lin+rin)/2 table 4. monoout switch configuration (01h: d5-d4) vcr1 vcr0 source of vcroutl/r 0 0 amp 0 1 tvin (default) 1 0 mute 1 1 (reserved) table 5. vcrout switch configuration
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 16 - 3. video block ? video switch control the AK4703 has switches for tv, vcr and rf modulator. each switch can be controlled via registers independently. when auto bit = ?1? or stby bit = ?1?, these switches setting is ignored and set to fixed configuration (loop-through mode). please refer the auto setup mode and standby mode. (04h: d2-d0) mode vtv2-0 bit source of tvvout pin source of tvrc pin source of tvg pin source of tvb pin shutdown 000 (hi-z) (hi-z) (hi-z) (hi-z) encoder cvbs /rgb 001 encv pin encrc pin encg pin encb pin encoder y/c 1 010 encv pin encrc pin hi-z (hi-z) encoder y/c 2 011 ency pin encc pin hi-z (hi-z) vcr (default) 100 vcrvin pin vcrrc pin vcrg pin vcrb pin tv cvbs 101 tvvin pin (hi-z) (hi-z) (hi-z) (reserved) 110 - - - - (reserved) 111 - - - - table 6. tv video output (please refer notes) (04h: d5-d3) mode vvcr2-0 bit source of vcrvout pin source of vcrc pin shutdown 000 (hi-z) (hi-z) encoder cvbs or y/c 1 001 encv pin encrc pin encoder cvbs or y/c 2 010 ency pin encc pin tv cvbs (default) 011 tvvin pin (hi-z) vcr 100 vcrvin pin vcrrc pin (reserved) 101 - - (reserved) 110 - - (reserved) 111 - - table 7. vcr video output (please refer notes) (04h: d7-d6) mode vrf1-0 bit source of rfv pin encoder cvbs1 00 encv pin encoder cvbs2 01 encg pin (note 2) vcr (default) 10 vcrvin pin shutdown 11 (hi-z) table 8. rf video output note 1. when input the video signal via encrc pin or vcrrc pin, set clamp1-0 bits respectively. note 2. when vtv2-0 bit = ?001?, tvg bit = ?1? and vrf1-0 bit = ?01?, rfv pin output is same as tvg pin output (encoder g).
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 17 - ? video output control (05h: d6-d0) each video output can be set to hi-z individually via control registers. these settings are ignored when the auto bit = ?1?. when the cio bit = ?1?, the vcrc pin outputs 0v even if the vcrc bit = ?0?. when the cio bit = ?0?, the vcrc pin follows the setting of vcrc bit. please refer the ?red/chroma bi-directional control for vcr scart?. tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control tvfb: tvfb output control 0: hi-z. (default) 1: active. ? red/chroma bi-directional control for vcr scart (05h: d7, d5) the 4703 supports the bi-directional red/chroma signal on the vcr scart. (AK4703) vc r r c pin vc r c pin vc r sc ar t 75 0.1u (cio bit & vcrc bit) #15 pin figure 5. red/chroma bi-directional control cio bit vcrc bit state of vcrc pin 0 0 hi-z (default) 0 1 active 1 0 connected to gnd 1 1 connected to gnd table 9. red/chroma bi-directional control
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 18 - ? clamp and dc-restore circuit control (06h: d6-d5, d3-d2) each cvbs and y input has the sync tip clamp circuit. the sync tip voltage at each output is 0.7v (typ). this corresponds 0.35v (typ) at the scart connector when matched by 75 ? resistors. the clamp1-0 bits select the input circuit for encrc pin (encoder red/chroma) and vcrrc pin (vcr red/chroma) respectively. vclp1-0 bits select the source of dc-restore circuit. clamp1: encoder red/chroma (encrc pin) input clamp control 0: dc restore clamp active (for red signal. default) 1: biased (for chroma signal.) clamp0: vcr r/c (vcrrc pin) input clamp control 0: dc restore clamp active (for red signal) 1: biased (for chroma signal. default.) vclp1-0: dc restore source control when the auto bit = ?1?, the source is fixed to vcrvin. vclp1 bit vclp0 bit sync source of dc restore 0 0 encv (default) 0 1 ency 1 0 vcrvin 1 1 (reserved) table 10. dc restore source control
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 19 - 4. blanking control the AK4703 supports fast blanking signals and slow blanking (function switching) signals for tv/vcr scart. ? input/output control for fast/slow blanking fb1-0: tv fast blanking output control (07h: d1-d0) fb1 bit fb0 bit tvfb pin output level 0 0 0v (default) 0 1 4v 1 0 same as vcr fb input (4v/0v) 1 1 (reserved) table 11. tv fast blanking output (note: minimum load is 150 ? ) sbt1-0: tv slow blanking output control (07h: d3-d2) sbt1 bit sbt0 bit tvsb pin output level 0 0 < 2v (default) 0 1 5v <, < 7v 1 0 (reserved) 1 1 10v < table 12. tv slow blanking output (note: minimum load is 10k ? ) sbv1-0: vcr slow blanking output control (07h: d5-d4) sbv1 bit sbv0 bit vcrsb pin output level 0 0 < 2v (default) 0 1 5v <, < 7v 1 0 (reserved) 1 1 10v < table 13. vcr slow blanking output (note: minimum load is 10k ? ) sbio1-0: tv/vcr slow blanking i/o control (07h: d7-d6) sbio1 bit sbio0 bit vcrsb pin direction tvsb pin direction 0 0 output (controlled by sbv1-0 bits) output (controlled by sbt1-0 bits) (default) 0 1 (reserved) (reserved) 1 0 input (stored in svcr1-0 bits) output (controlled by sbt1-0 bits) 1 1 input (stored in svcr1-0 bits) output (same output as vcr sb) table 14. tv/vcr slow blanking i/o control
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 20 - 5. monitor options and int function ? monitor options (08h: d4-d0) the AK4703 has several monitors for the input dc level of vcr slow blanking, the input dc level of vcr fast blanking and signals input to tvvin or vcrvin pins. svcr1-0 bits, fvcr bit, vcmon bit and tvmon bit are reflected to these values. svcr1-0: vcr slow blanking status monitor svcr1-0 bits reflect the voltage at vcrsb pin only when the vcrsb is in the input mode. when the vcrsb is in the output mode, svcr1-0 bits hold previous value. vcrsb pin input level svcr1 bit svcr0 bit < 2v 0 0 4.5 to 7v 0 1 (reserved) 1 0 9.5 < 1 1 table 15. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. vcrfb pin input level fvcr bit < 0.4v 0 1v < 1 table 16. vcr fast blanking monitor (typical threshold is 0.7v) vcmon: vcr input monitor 0: no video signal detected via vcrvin pin. 1: detects video signal via vcrvin pin. tvmon: tv input monitor 0: no video signal detected via tvvin pin. 1: detects video signal via tvvin pin.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 21 - ? int function and mask options (09h: d3-d1) changes of the 08h status can be monitored via the int pin. the int pin is the open drain output and goes ?l? for 2 s (typ.) when the status of 08h is changed. this pin should be connected to vd (typ. 5v) through 10k ? resistor. mvc bit, mtv bit, mfvcr bit and msvcr bit control the reflec tion of the status change of these monitors onto the int pin from report to prevent to masks each monitor. mvc: vcr input monitor mask auto bit mvc bit reflection of the change of vcmon bit to int pin 0 0 reflect 0 1 not reflect (e.g. masked) 1 0 reflect 1 1 reflect (default ) table 17. reflection of vcmon change mtv: tv input monitor mask auto bit mtv bit reflection of the change of tvmon bit to int pin 0 0 reflect 0 1 not reflect (e.g. masked) 1 0 reflect 1 1 reflect (default ) table 18. reflection of tvmon change mfvcr: fvcr monitor mask 0: change of mfvcr is reflected to int pin. (default) 1: change of mfvcr is not reflected to int pin. msvcr: svcr1-0 monitor mask 0: change of svcr1-0 is reflected to int pin. (default) 1: change of svcr1-0 is not reflected to int pin.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 22 - 6. control interface i 2 c-bus control mode 1. write operations figure 6 shows the data transfer sequence in i 2 c-bus mode. all commands are preceded by a start condition. a high to low transition on the sda line while scl is high indicates a start condition (figure 12). after the start condition, a slave address is sent. this address is 7bits long followed by an eighth bit that is a data direction bit (r/w). the most significant seven bits of the slave address are fixed as ?0010001?. if the slave address match that of the AK4703, the AK4703 generates the acknowledge and the operation is executed. the master must generate the acknowledge-related clock pulse and release the sda line (high) during the acknowledge clock pulse (figure 13). a ?1? for r/w bit indicates that the read operation is to be executed. a ?0? indicates that the write operation is to be executed. the second byte consists of the address for control registers of the AK4703. the format is msb first, and those most significant 3-bits are fixed to zeros (figure 8). the data after the second byte contain control data. the format is msb first, 8bits (figure 9). the AK4703 generates an acknowledge after each byte has been received. a data transfer is always terminated by a stop condition generated by the master. a low to high transition on the sda line while scl is high defines a stop condition (figure 12). the AK4703 can execute multiple one byte write operations in a sequence. after receipt of the third byte, the AK4703 generates an acknowledge, and awaits the next data again. the master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 09h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (figure 14) except for the start and the stop condition. sda s t a r t a c k a c k s slave a ddress a c k sub a ddress(n) data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k figure 6. data transfer sequence at the i 2 c-bus mode 0 0 1 0 0 0 1 r/w figure 7. the first byte 0 0 0 a4 a3 a2 a1 a0 figure 8. the second byte d7 d6 d5 d4 d3 d2 d1 d0 figure 9. byte structure after the second byte
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 23 - 2. read operations set r/w bit = ?1? for read operations. after transmission of data, the master can read the next address?s data by generating an acknowledge instead of terminating the write cycle after the receipt the first data word. after the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. if the address exceeds 09h prior to generating the stop condition, the address counter will ?roll over? to 00h and the previous data will be overwritten. the AK4703 supports two basic read operations: current address read and random read. 2-1. current address read the AK4703 contains an internal address counter that maintain s the address of the last word accessed, incremented by one. therefore, if the last access (either a read or writ e) was to address n, the next current read operation would access data from the address n+1. after receipt of the slave address with r/w bit set to ?1?, the AK4703 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4703 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n+1) p s t o p data(n+x) a c k data(n+2) a c k r/w= ?1? a c k data(n) figure 10. current address read 2-2. random read random read operation allows the master to access any memory location at random. prior to issuing the slave address with the r/w bit set to ?1?, the master must first perform a ?dummy? write operation. the master issues a start condition, slave address (r/w bit = ?0?) and then the register address to read. after the register?s address is acknowledge, the master immediately reissues the start condition and the slave address with the r/w bit set to ?1?. then the AK4703 generates an acknowledge, 1-byte data and increments the internal address counter by 1. if the master does not generate an acknowledge to the data but generate the stop condition, the AK4703 discontinues transmission. sda s t a r t a c k a c k s slave a ddress a c k data(n) p s t o p data(n+x) a c k data(n+1) a c k r/w= ?0? a c k sub a ddress(n) s t a r t a c k s slave a ddress r/w= ?1? figure 11. random address read
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 24 - scl sda stop condition start condition s p figure 12. start and stop conditions scl from master acknowledge data output by transmitter data output by receiver 1 9 8 start condition not acknowledge clock pulse for acknowledgement s 2 figure 13. acknowledge on the i 2 c-bus scl sda data line stable; data valid change of data allowed figure 14. bit transfer on the i 2 c-bus
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 25 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 auto amppd bias stby 01h switch mute 0 vcr1 vcr0 mono 0 tv1 tv0 02h reserved 0 0 0 0 0 0 0 0 03h zerocross 0 vmono 0 0 0 zero ztm1 ztm0 04h video switch vrf1 vrf0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 05h video output enable cio tvfb vcrc vcrv tvb tvg tvr tvv 06h video volume/clamp 0 vclp1 vclp0 0 clamp1 clamp0 0 0 07h s/f blanking control sbio1 sbio 0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 08h s/f blanking monitor 0 0 0 tvmon vcmon fvcr svcr1 svcr0 09h monitor mask 0 0 0 mtv mvc mfvcr msvcr 0 when the pdn pin goes ?l?, the registers are initialized to their default values. while the pdn pin = ?h?, all registers can be accessed. do not write any data to the register over 09h.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 26 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 0 0 0 0 auto amppd bias stby r/w r/w default 0 0 0 0 1 1 1 1 stby: standby control 0: normal operation 1: standby mode (default). all registers are not initialized. dac : powered down and timings are reset. source of tvout : fixed to vcrin, source of vcrout : fixed to tvin, source of monoout : fixed to vcrin, source of tvvout : fixed to vcrvin (or hi-z), source of tvrc : fixed to vcrrc (or hi-z), source of tvg : fixed to vcrg (or hi-z), source of tvb : fixed to vcrb (or hi-z), source of vcrvout : fixed to tvvin (or hi-z), source of vcrc : fixed to hi-z or vss (controlled by cio bit). bias: audio output control 0: normal operation 1: all audio outputs to gnd (default) amppd: amp power down control 0: normal operation 1: amp power down (default) auto: auto startup bit 0: auto startup disable (manual startup). 1: auto startup enable (default). note: when the sbio1 bit = ?1?(default = ?0?), the change of auto bit may cause a ?l? pulse on int pin.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 27 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h switch mute 0 vcr1 vcr0 mono 0 tv1 tv0 r/w r/w default 1 0 0 1 0 0 0 1 tv1-0: tvoutl/r pins source switch 00: amp 01: vcrinl/r pins (default) 10: mute 11: lin/rin mono: mono select for tvoutl/r pins 0: stereo. (default) 1: mono. (l+r)/2 vcr1-0: vcroutl/r pins source switch 00: amp 01: tvinl/r pins (default) 10: mute 11: reserved mute: mute switch 0: normal operation 1: mute (default) when mute bit = ?1?, tvoutl/r outputs vcom voltage after tvoutl/r output is zero-crossing. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h selector 0 0 0 0 0 msel 0 0 r/w r/w default 0 0 0 0 0 1 0 0 msel: selector for monoout pin 0: mixed output of amp 1: mixed output of tv1-0 switch (default)
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 28 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h zerocross 0 vmono 0 0 0 zero ztm1 ztm0 r/w r/w default 0 0 0 0 0 1 0 0 ztm1-0: the time length control of zero-cross timeout 00: typ. 10ms (default) 01: typ. 20ms 10: typ. 40ms 11: typ. 80ms zero: zero-cross detection enable for tvout output 0: disable the tvout outputs vcom voltage immediately without zero-cross when mute bit is ?1?. 1: enable (default) the tvout outputs vcom voltage when timeout or zero-cross before timeout when mute bit is ?1?. vmono: mono select for vcroutl/r pins 0: stereo. (default) 1: mono. (l+r)/2 addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h video switch vrf1 vrf0 vvcr2 vvcr1 vvcr0 vtv2 vtv1 vtv0 r/w r/w default 1 0 0 1 1 1 0 0 vtv2-0: selector for tv video output please refer the table 6. vvcr2-0: selector for vcr video output please refer the table 7. vrf1-0: selector for rfv pin output please refer the table 8.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 29 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h output enable cio tvfb vcrc vcrv tvb tvg tvr tvv r/w r/w default 0 0 0 0 0 0 0 0 tvv: tvvout output control tvr: tvrcout output control tvg: tvgout output control tvb: tvbout output control vcrv: vcrvout output control vcrc: vcrc output control (please refer the table 9) tvfb: tvfb output control 0: hi-z (default) 1: active. when the cio pin = ?h?, the vcrc pin is connected to gnd even if vcrc bit = ?0?. when the cio pin = ?l?, the vcrc pin follows the setting of vcrc bit. cio: vcrc pin i/o control please refer the table 9. addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h video volume 0 vclp1 vclp0 0 clamp1 clamp0 0 0 r/w r/w default 0 0 0 0 0 1 0 0 clamp1: encoder r/chroma (encrc pin) input clamp control 0: dc restore clamp active (for red signal. default) 1: biased (for chroma signal.) clamp0: vcr r/c (vcrc pin) input clamp control 0: dc restore clamp active (for red signal) 1: biased (for chroma signal. default.) vclp1-0: dc restore source control 00: encv pin (default) 01: ency pin 10: vcrvin pin 11: (reserved) when the auto bit = ?1?, the source is fixed to vcrvin pin.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h s/f blanking sbio1 sbio0 sbv1 sbv0 sbt1 sbt0 fb1 fb0 r/w r/w default 0 0 0 0 0 0 0 0 fb1-0: tv fast blanking output control (for tvfb pin) 00: 0v (default) 01: 4v 10: follow vcr fb input (4v/0v) 11: (reserved) sbt1-0: tv slow blanking output control (for tvsb pin. minimum load is 10k ? .) 00: < 2v (default) 01: 5v <, < 7v 10: (reserved) 11: 10v < sbv1-0: vcr slow blanking output control (for vcrsb pin. minimum load is 10k ? .) 00: < 2v (default) 01: 5v <, < 7v 10: (reserved) 11: 10v < sbio1-0: tv/vcr slow blanking i/o control (please refer the table 14.)
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 31 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h sb/fb monitor 0 0 0 tvmon vcmon fvcr svcr1 svcr0 r/w read default 0 0 0 0 0 0 0 0 svcr1-0: vcr slow blanking status monitor svcr1-0 bits reflect the voltage at vcrsb pin only when the vcrsb is in the input mode. when the vcrsb is in the output mode, svcr1-0 bits hold previous value. vcrsb pin input level svcr1 bit svcr0 bit < 2v 0 0 4.5 to 7v 0 1 (reserved) 1 0 9.5 < 1 1 table 19. vcr slow blanking monitor fvcr: vcr fast blanking input level monitor this bit is enabled when tvfb bit = ?1?. vcrfb pin input level fvcr bit < 0.4v 0 1v < 1 table 20. vcr fast blanking monitor (typical threshold is 0.7v) vcmon: vcr input monitor 0: no video signal detected via vcrvin pin. 1: detects video signal via vcrvin pin. tvmon: tv input monitor 0: no video signal detected via tvvin pin. 1: detects video signal via tvvin pin.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 32 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 09h monitor mask 0 0 0 mtv mvc mfvcr msvcr 0 r/w r/w default 0 0 0 0 1 0 0 0 msvcr: svcr1-0 bits monitor mask 0: the int pin reflects the change of svcr1-0 bit. (default) 1: the int pin does not reflect the change of svcr1-0 bits. mfvcr: fvcr monitor mask 0: the int pin reflects the change of mfvcr bit. (default) 1: the int pin does not reflect the change of mfvcr bit. mvc: vcr input monitor mask please refer the table 17. mtv: tv input monitor mask please refer the table 18.
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 33 - system design tbd figure 15. typical connection diagram
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 34 - ? grounding and power supply decoupling vd, vp, vvd1, vvd2, vss and vvss should be supplied from analog supply unit with low impedance and be separated from system digital supply. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these pins to eliminate the effects of high frequency noise. the 0.1 f ceramic capacitor should be placed as near to vd (vp, vvd1, vvd2) as possible. ? voltage reference each dvcom/pvcom are signal ground of this chip. an electrolytic capacitor 10 f parallel with a 0.1 f ceramic capacitor should be attached to these vcom pins to eliminat e the effects of high frequency noise. no load current may be drawn from these vcom pins. all signals, especially clocks, should be kept away from these vcom pins in order to avoid unwanted coupling into the AK4703. ? analog audio outputs the analog outputs are also single-ended and centered on 5.6v(typ.). the output signal range is typically 2vrms (typ@vd=5v).
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 35 - ? external circuit example analog audio input pin monoin tvinl/r vcrinl/ r a mpl/ r 0.47f 300ohm (cable) analog audio output pin monoout tvoutl/r vcroutl/r 10f 300ohm total > 4.5kohm (cable) analog video input pin encv, ency, vcrvin, tvvin, encrc, encc, vcrrc, encg, vcrg, encb, vcrb 0.1f 75ohm (cable) 75ohm analog video output pin tvvout, tvrc tvg, tvr, rfv vcrvout, vcrc max 400pf 75ohm 75ohm max 15pf (cable)
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 36 - slow blanking pin tvsb vcrsb max 3nf (with 400ohm) 400ohm (max 500ohm) min: 10k ohm (cable) fast blanking input pin vcrfb 75ohm (cable) 75ohm fast blanking output pin tvfb 75ohm 75ohm (cable)
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 37 - package tbd ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei akm confidential [AK4703] rev. 0.1 2004/03 - 38 - marking tbd xxxxxxxx: date code identifier important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulati ons of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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